Design of low power high speed VLSI adder subsystem

The design of adder subsystem is the most focused area in VLSI design of processing units. So far there are a variety of such adders like RCA, CSA, CLA and ETA. ETA is the Error Tolerant Adder and is the latest of the adders which has better performance when compared with the other adders in terms of power consumption, delay etc. Whereas the designs so far is by front end tools that performs simulations with ideal parameters instead of real time conditions. So, here in this paper, the design is approached through backend tool under real time simulation conditions. The results showed that the adder performance in terms of accuracy, delay, size and with 70% lesser power consumption than that of the conventional c-MOS adders.

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