Hardware/software selected cycle solution

For many system designs where hardware and software are co-dependent, there often exists a design bottleneck where most of the hardware design has to be completed and fabricated before meaningful software verification can begin. In some sectors of electronic design where competitive markets require that the design cycle has to be completed quickly-mobile phone handsets and image decoders, for instance-having the software ready and substantially debugged as soon as the hardware is ready can give a significant competitive advantage. This paper describes a methodology that allows practical hardware/software co-simulation to achieve meaningful software verification early in the design cycle. The technique allows software development and testing to be more concurrent with the hardware development by using simulated models of the hardware design to interact with the software programs. A high level of performance is achieved by using the simulated description on selected target processor cycles only. Only the important bus cycles are simulated in the hardware simulator.<<ETX>>