The performance measure of GS-DG MOSFET: an impact of metal gate work function

The quantitative assessment of the nanoscale gate stack double gate (GS-DG) MOSFET performance values are numerically calculated with different gate metal work functions (Φ m = 4.52 eV, 4.6 eV, 4.7 eV). The effect of electrostatic control on dc, analog and RF figures of merit (FOMs) which includes subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance generation factor (TGF), early voltage (V EA), intrinsic gain (AV), cut off frequency (f T) and transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) have been investigated for the model GS-DG MOSFET. Higher TGF and AV was achieved with Φ m = 4.6 eV for the device. For a better comparison among the analog/RF FOMs, the threshold voltage (V th) is maintained at a constant value for different work function cases. To achieve a constant V th, the channel doping (NA) and source/drain doping (ND) is tuned accordingly for all device cases. Superior f T which is due to higher transconductance (g m) and lower output conductance (g d), was observed for the device. In addition, better gain performances i.e. GFP and GTFP were achieved resulting from improved g m. Thus, the device structure modelled with Φ m of 4.6 eV can be considered as a better candidate for analog and RF circuit applications.

[1]  M. J. Kumar,et al.  Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review , 2004, IEEE Transactions on Device and Materials Reliability.

[2]  Y. Taur,et al.  A continuous, analytic drain-current model for DG MOSFETs , 2004 .

[3]  M. Bucher,et al.  Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs , 2012, IEEE Transactions on Nanotechnology.

[4]  C.K. Sarkar,et al.  Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs , 2010, IEEE Transactions on Electron Devices.

[5]  L. Register,et al.  Graphene field-effect transistors , 2011 .

[6]  Chandan Kumar Sarkar,et al.  Effect of gate engineering in double-gate MOSFETs for analog/RF applications , 2012, Microelectron. J..

[7]  Abhinav Kranti,et al.  Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications , 2004 .

[8]  G. Ghibaudo,et al.  Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs , 2008, IEEE Transactions on Electron Devices.

[9]  C. Hu,et al.  A comparative study of advanced MOSFET concepts , 1996 .

[10]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[11]  H.-S. Philip Wong.  Beyond the conventional transistor , 2002, IBM J. Res. Dev..

[12]  Chandan Kumar Sarkar,et al.  Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications , 2009, Microelectron. Reliab..

[13]  M. Gupta,et al.  TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET , 2011, IEEE Transactions on Electron Devices.

[14]  Y. Tosaka,et al.  Scaling theory for double-gate SOI MOSFET's , 1993 .

[15]  A. Mallik,et al.  Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications , 2012, IEEE Transactions on Electron Devices.

[16]  Karen Willcox,et al.  Kinetics and kinematics for translational motions in microgravity during parabolic flight. , 2009, Aviation, space, and environmental medicine.

[17]  Denis Flandre,et al.  Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .

[18]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs , 2004 .

[19]  S. Chakraborty,et al.  Subthreshold Performance of Dual-Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications , 2008, IEEE Transactions on Electron Devices.

[20]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[21]  Chenming Hu,et al.  An adjustable work function technology using Mo gate for CMOS devices , 2002, IEEE Electron Device Letters.

[22]  Rong Zhang,et al.  Field-effect transistors based on two-dimensional materials for logic applications , 2013 .

[23]  Sorin Cristoloveanu,et al.  Frontiers of silicon-on-insulator , 2003 .

[24]  Jeffrey Bokor,et al.  Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.