On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation

As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. This paper presents a VLSI architecture that can be configured to compute the SAD of 4×4 pixel blocks with no subsampling or with 2:1 or 4:1 subsampling (pel decimation). The proposed architecture was synthesized for 130nm, 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and a given target throughput. The impacts of subsampling and Low-Vdd/High-Vt on delay, power and energy efficiency are analyzed. In a total of 16 syntheses, the 45nm/LH configurable SAD architecture achieved the highest energy efficiency for target frequency when operating in pel decimation 4:1, spending only 2.19pJ for each 4×4 block, which corresponds to about 20.64 times less energy than the 130nm/nominal configurable architecture operating in full SAD mode. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when 2:1 and 4:1 subsamplings are chosen, respectively, in the configurable architecture.

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