Hybrid BIST Optimization Using Reseeding and Test Set Compaction

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems.

[1]  Nur A. Touba,et al.  Test point insertion based on path tracing , 1996, Proceedings of 14th VLSI Test Symposium.

[2]  Makoto Sugihara,et al.  Analysis and minimization of test time in a combined BIST and external test approach , 2000, DATE '00.

[3]  Nur A. Touba,et al.  Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[4]  Raimund Ubar,et al.  A hybrid BIST architecture and its optimization for SoC testing , 2002, Proceedings International Symposium on Quality Electronic Design.

[5]  Gundolf Kiefer,et al.  Application of Deterministic Logic BIST on Industrial Circuits , 2001, J. Electron. Test..

[6]  Raimund Ubar,et al.  Energy minimization for hybrid BIST in a system-on-chip test environment , 2005, European Test Symposium (ETS'05).

[7]  Erik G. Larsson,et al.  Introduction to Advanced System-on-Chip Test Design and Optimization , 2005 .

[8]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[9]  Petru Eles,et al.  Hybrid BIST time minimization for core-based systems with STUMPS architecture , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[10]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[11]  Peter Harrod,et al.  Testing reusable IP-a case study , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[12]  David Flynn,et al.  AMBA: enabling reusable on-chip designs , 1997, IEEE Micro.

[13]  D.P. Siewiorek,et al.  Testing of digital systems , 1981, Proceedings of the IEEE.

[14]  Yervant Zorian,et al.  Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[15]  Nur A. Touba,et al.  BETSY: synthesizing circuits for a specified BIST environment , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[16]  Raimund Ubar,et al.  Hybrid BIST energy minimisation technique for system-on-chip testing , 2006 .

[17]  Solomon W. Golomb,et al.  Shift Register Sequences , 1981 .

[18]  Yervant Zorian,et al.  Challenges in testing core-based system ICs , 1999, IEEE Commun. Mag..

[19]  Charles R. Kime,et al.  MFBIST: a BIST method for random pattern resistant circuits , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[20]  R. Ubar,et al.  Optimization of the Store-and-Generate Based Built-in Self-Test , 2006, 2006 International Biennial Baltic Electronics Conference.

[21]  Fabrizio Lombardi,et al.  Analysis and measurement of fault coverage in a combined ATE and BIST environment , 2004, IEEE Transactions on Instrumentation and Measurement.

[22]  Raimund Ubar,et al.  Test cost minimization for hybrid BIST , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[23]  Petru Eles,et al.  Test Time Minimization for Hybrid BIST of Core-Based Systems , 2006, Journal of Computer Science and Technology.

[24]  R. Schaller,et al.  Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).

[25]  Petr Fiser.  Pseudo-Random Pattern Generator Design for Column-Matching BIST , 2007 .