Nanopower Subthreshold MCML in Submicrometer CMOS Technology

This paper presents subthreshold MOS current-mode logic (MCML) circuits implemented in a commercial 0.25-mum CMOS technology. We propose the adoption of bulk-drain-connected pMOS transistors as loads for subthreshold MCML gates. The b-d connection extends the linear operating range of the load, thus increasing the output logic swing of the subthreshold MCML gate. Theoretical and measured results are presented for an MCML inverter and a ten-stage ring oscillator operating at supply voltages below the threshold-voltage value, with power consumption on the order of nanowatts. At a 300-mV supply, the oscillator works at a frequency of 638 Hz with a total power consumption of 345 pW.

[1]  Massimo Alioto,et al.  Design strategies for source coupled logic gates , 2003 .

[2]  Armin Tajalli,et al.  Ultra-low power subthreshold current-mode logic utilising PMOS load device , 2007 .

[3]  Francisco Serra-Graells,et al.  Sub-1-V CMOS proportional-to-absolute temperature references , 2003, IEEE J. Solid State Circuits.

[4]  S. Bruma Impact of on-chip process variations performance on MCML [MOS current mode logic] , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[5]  Masayuki Mizuno,et al.  A GHz MOS adaptive pipeline technique using MOS current-mode logic , 1996, IEEE J. Solid State Circuits.

[6]  Christofer Toumazou,et al.  Nano-power subthreshold current-mode logic in sub-100 nm technologies , 2005 .

[7]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[8]  克里斯特弗·图马佐,et al.  Current mode logic digital circuits , 2006 .

[9]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[10]  Tetsuo Endoh,et al.  0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation , 2001, IEEE J. Solid State Circuits.

[11]  A. Tajalli,et al.  Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[12]  Mohamed I. Elmasry,et al.  MOS current mode circuits: analysis, design, and variability , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  A. Tajalli,et al.  Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications , 2008, IEEE Journal of Solid-State Circuits.

[14]  Eric A. Vittoz The Design of High-Performance Analog Circuits on Digital CMOS Chips , 1985 .

[15]  Massimo Alioto,et al.  Nanometer MCML gates: models and design considerations , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[16]  Christofer Toumazou,et al.  Bulk-drain connected load for subthreshold MOS current-mode logic , 2007 .

[17]  Andreas G. Andreou,et al.  Current-mode differential logic circuits for low power digital systems , 1996, Proceedings of the 39th Midwest Symposium on Circuits and Systems.

[18]  Masakazu Yamashina,et al.  An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors , 1992 .

[19]  E. Vittoz,et al.  An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .

[20]  Jan M. Rabaey,et al.  MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[21]  Mile K. Stojcev Low Power Electronics Design, Christian Pignet, Editor, CRC Press, Boca Raton, 2005, Hardcover, pp 854, plus 18, ISBN 0-8493-1941-2 , 2006, Microelectron. Reliab..