FPGA Designs of Channel Encoder and Decoder for IEEE802.11n
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The principle of convolutional encoding and Viterbi decoding for next generation WLAN standard IEEE802.11n is analyzed.The FPGA implementation methods of convolutional encoder and Viterbi decoder are presented,in which the Viterbi decoder employs the parallel structure and traceback decoding algorithm to improve performance.The simulation results show that the maximum clock frequency of the Viterbi decoder can achieve 286 MHz,which is feasible for IEEE 802.11n system.