Design Of High Frequency Digital Phase Locked Loops

This paper considers the stability of high order Charge Pump Phase Lock Loop (CP-PLL), proposing a novel means of identifying stable regions for such systems. Traditional design techniques are inefficient for high frequency, high ord er CPPLL systems. This paper proposes an accurate and efficient means of identifying stable regions for 2 nd and 3 rd order high frequency (> 1GHz) CP-PLL. Using exact non-linear CP-PLL responses it is shown that the proposed stability tech nique is a significant improvement over existing linear methods.

[1]  S. Williamson.  How to design RF circuits-synthesisers , 2000 .

[2]  Maher Rizkalla,et al.  Maximizing the stability region for a second order PLL system , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

[3]  Roland E. Best.  Phase-locked loops : design, simulation, and applications , 2003 .

[4]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[5]  N. E. Wu.  Analog phaselock loop design using Popov criterion , 2002, Proceedings of the 2002 American Control Conference (IEEE Cat. No.CH37301).

[6]  A. Rantzer.  Almost global stability of phase-locked loops , 2001, Proceedings of the 40th IEEE Conference on Decision and Control (Cat. No.01CH37228).

[7]  Dean Banerjee,et al.  Pll Performance, Simulation, and Design , 2003 .

[8]  Ronan Farrell,et al.  ARBITRARY ORDER CHARGE APPROXIMATION EVENT DRIVEN PHASE LOCK LOOP MODEL , 2004 .

[9]  Shahriar Mirabbasi,et al.  Design of loop filter in phase-locked loops , 1999 .

[10]  An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL ’ s , 2001 .

[11]  D. Abramovitch,et al.  Lyapunov redesign of classical digital phase-lock loops , 2003, Proceedings of the 2003 American Control Conference, 2003..

[12]  J.G. van de Groenendaal,et al.  Phase-plane analysis of phase-locked loops used for clock recovery , 1994, Proceedings of COMSIG '94 - 1994 South African Symposium on Communications and Signal Processing.

[13]  Moisés Simões Piedade,et al.  High performance analog and digital PLL design , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).