Design Of High Frequency Digital Phase Locked Loops

This paper considers the stability of high order Charge Pump Phase Lock Loop (CP-PLL), proposing a novel means of identifying stable regions for such systems. Traditional design techniques are inefficient for high frequency, high ord er CPPLL systems. This paper proposes an accurate and efficient means of identifying stable regions for 2 nd and 3 rd order high frequency (> 1GHz) CP-PLL. Using exact non-linear CP-PLL responses it is shown that the proposed stability tech nique is a significant improvement over existing linear methods.

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