Dark Count Rate (DCR) in Single-Photon Avalanche Diodes (SPAD) in Complementary Metal-Oxide Semiconductor technology is characterized and analyzed with a comprehensive simulation methodology. Based on a series of measurements of SPAD with various architectures, on an extended range of voltages and temperatures, the DCR measurements are correlated to the spatial localization of traps within the device and their parameters. To this aim, process and electrical simulations using Technology Computer-Aided Design (TCAD) tools are combined with an in-house McIntyre solver to compute the breakdown probability (Pi). The traps are accounted for using thermal SRH carrier generation-recombination mechanism which is coupled with the position-dependent breakdown probability. This rigorous methodology makes it possible to directly compare with DCR measurements, since only generated carriers with a non-negligible breakdown probability are considered.