Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells

A methodology relating physical features of point defects inherent in the fabrication process to the circuit-level faulty behaviors caused by these defects is proposed. A simulation approach to support this methodology is introduced and illustrated using an example n-MOS circuit. Using this methodology, technology and layout dependent faults can be generated and ranked according to their likelihood. Using a ranked fault list, a new and more effective testing approach for MOS VLSI circuits can be developed.