Multiple Word Length based low power digital base band receiver

In recent years power consumption in CMOS VLSI circuits has become a major design constraint. This is in particular important for mobile wireless communication systems, due to the limited life time of the batteries to power wireless communication equipment. The circuit designers came with suitable low power strategies to achieve low power design. These circuit level techniques are readily available in the form of standard cells to the Register Transfer Level (RTL) designer. Currently designers are exploring the algorithm level and architecture level techniques towards arriving at low power communication Integrated Circuits (ICs). The Word Length Optimization (WLO) is an algorithmic approach with promising power saving levels, suitable for communication applications. The work presented here demonstrates power optimized RTL design for wireless base band receiver using Quadrature Phase Shift Keying (QPSK) modulation scheme. The novel method of arriving at suitable word lengths based on system level parameters at each signal stage is demonstrated. The Symbol Error Rates (SER) for given energy per symbol are analyzed. The Xilinx Zynq-7 Family FPGA is used for area, power and performance analysis. The peak power optimization of 40% is reported for Es/No = 8 dB, in comparison to the normal design.

[1]  Partha Pratim Bhattacharya,et al.  Design of Low Power Wake-up Receiver for Wireless Sensor Network , 2014 .

[2]  George A. Constantinides.  Perturbation analysis for word-length optimization , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[3]  Ömer Özdil,et al.  Automated fixed-point precision optimization , 2012, 2012 20th Signal Processing and Communications Applications Conference (SIU).

[4]  Daniel Ménard,et al.  Novel algorithms for word-length optimization , 2011, 2011 19th European Signal Processing Conference.

[5]  M. Madhavi Latha,et al.  An optimum ADC output word length selection for low power communication architectures , 2013, 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[6]  Navakanta Bhat,et al.  Power Scalable Radio Receiver Design Based on Signal and Interference Condition , 2012 .

[7]  O. Sarbishei,et al.  Challenges in verifying and optimizing fixed-point arithmetic-intensive designs , 2010, 2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR).

[8]  Paul Chow,et al.  Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy , 2008, TECS.

[9]  S. Ramakrishnan,et al.  Exploiting signal and noise statistics for fixed point FFT design optimization in OFDM systems , 2010, 2010 National Conference On Communications (NCC).

[10]  D. Jackuline Moni,et al.  Design of low power and high speed configurable booth multiplier , 2011, 2011 3rd International Conference on Electronics Computer Technology.

[11]  Gabriel Caffarena,et al.  Fast fixed-point optimization of DSP algorithms , 2010, VLSI-SoC.

[12]  Rekha Masanam,et al.  Area Efficient Fft/Ifft Processor for Wireless Communication , 2014 .

[13]  Peter E. Buxa,et al.  Optimize hardware with fixed-point variable length phase factors , 2012, 10th IEEE International NEWCAS Conference.

[14]  O. Sarbishei,et al.  Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Gabriel Caffarena Fernández.  Combined Word-Length Allocation and High-Level Synthesis of Digital Signal Processing Circuits , 2008 .

[16]  E. Sedano,et al.  Acceleration of Monte-Carlo simulation-based quantization of DSP systems , 2012, 2012 19th International Conference on Systems, Signals and Image Processing (IWSSIP).