Laser : a layout sensitivity explorer : report and user's manual

As the IC pattern resolutions tend 10 become smaller the layout geometry plays a more important role in IC yield. The probability that a chip will fail is directly related to the way that the IC artwork is laid out. By examining the possible places where catastrophic defects may occur one can prevent potential faults, and thus estimate the reliability of the design. Rrealistic yield simulation tools must consider the specific layout. It is, therefore, ideal a CAE tool that automatically explores and predicts the layout reliability for real environmentai conditions prevailing in the manufacturing line. We present a system capable of interactively finding the critical areas for shorts and breaks, the sensitivity, and the yield of the IC artwork,for any range of defect sizes. The implementation is based on a simple scanline algorithm and performs only one layout extraction for any span of defect sizes

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