Guest editors' introduction - Special issue on FPGAs: applications and designs

Reconfiguration of circuitry at runtime to suit the application at hand has created a promising paradigm of computing that blurs traditional frontiers between software and hardware. This powerful computing paradigm, named reconfigurable computing (or custom computing), is based on the use of field-programmable logic devices, mainly field-programmable gate arrays (FPGAs), incorporated in board-level reconfigurable systems. FPGAs have the benefits of the hardware speed and the software flexibility; also, they have a price/performance ratio much more favourable than ASICs (Application-Specific Integrated Circuits). For these reasons, FPGAs are a good alternative for many real applications in image and signal processing, multimedia, robotics, telecommunications, cryptography, networking and computation in general. This Special Issue brings together high-quality state-of-the-art contributions about FPGAs applications and designs. Since the early years of programmable logic arrays, FPGA research has experienced tremendous growth in both academic and industrial organizations. As a result, at present, FPGAs are very popular devices in many different fields. As an example of the current interest in FPGAs, it is worth mentioning that for this Special Issue we have received more than 65 high-quality submissions from many different countries. This Special Issue contains 12 papers that represent the diverse applications and designs being addressed today by the FPGA research community. With authors from around the world, these articles bring us an international sampling of significant work. The title of our first paper is ‘FPGA-based Implementation of Recursive Algorithms’, by V. Sklyarov. This paper clearly demonstrates that FPGAs are blurring traditional frontiers between software and hardware. The author suggests a novel method for implementing recursive algorithms in hardware. In this article, the required support for recursion has been provided through a modular and a hierarchical specification of a control unit that can be translated to an implementation of the respective hardware circuit on the basis of a recursive hierarchical finite state machine and through a mechanism that permits the contents of an execution unit to be stored/restored between hierarchical calls/returns. As an example, the paper studies in detail two practical applications of recursive algorithms in the data sorting and compression area. The second paper, ‘Case Study of a Functional Genomics Application for an FPGA-based Coprocessor’ by T.V. Court, M.C. Herbordt, and R.J. Barton, points to a new area of applicability of FPGA coprocessors: the functional genomics. Microarrays measure simultaneously the expression products of thousands of genes in a tissue sample and so are being used to investigate a number of critical biology questions. Although microarrays are already having a tremendous impact on biomedical science, they still present great computational challenges. For this reason, this article proposes the use of an FPGAbased coprocessor. Our third paper ‘An FPGA-based Queue Management System for High Speed Networking Devices’ authored by A. Nikologiannis, I. Papaefstathiou, G. Kornaros, and C. Kachris states the importance of FPGAs in network and telecommunications systems. In these systems, one of the main bottlenecks is very often its memory subsystem, mainly due to the extremely high speed of the state-ofthe-art network links and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. This paper describes the architecture and performance of a memory manager, the QMS (Queue Management System) that is tailored to FPGA technology and can provide up to 6.2 Gbps of aggregate throughput, while handling 32K independent queues. The network systems are also addressed in the fourth paper, ‘FPGA Implementation and Experimental Evaluation of a Multizone Network Cache’ by P. Berube, M. MacGregor, and J. Nelson-Amaral. This paper presents the FPGA implementation and evaluation of a versatile prototype of a Content Addressable Memory (CAM). Network routers rely on CAMs to accelerate the process of looking up the next hop of a packet. In any case, this