Design of High Performance Compute Node for Belle II Pixel Detector Data Acquisition System

Belle II Pixel Detector (PXD) is a new designed silicon pixel detector on Belle II upgrade. It generate up to 240 Gbit data per second. With the help of Silicon Vertex Detector (SVD) and other detectors, PXD data will reduce to 1/30. High Performance Compute Node (CN) is used as the central board of PXD Data Acquisition (DAQ) System. Intelligent Platform Management Controller and Module Management Controller (IPMC/MMC) are used to monitor power consumption, temperature and firmware download. Final version of Compute Node is finished in 2015 and successfully joined beam test with PXD, SVD, frond-end readout part and High Level Trigger (HLT) in DESY in Jan. 2017.