Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Floating-gate (FG)-type tri-gate flash memories with an improved inter-poly dielectric (IPD) layer have been successfully fabricated by introducing a newly developed rapid thermal oxidation (RTO) process, and their NOR-mode operation including threshold voltage (Vt) variations before and after one program/erase (P/E) cycle have been systematically investigated. It was experimentally confirmed that the gate breakdown voltage (BVg) is greatly increased from 12 to 19 V by introducing the RTO process thanks to the high quality and thin thermal silicon dioxide (SiO2) formation on the FG surface and etched edge regions, which effectively blocks the leakage pass of the IPD layer. A source–drain (SD) breakdown voltage (BVDS) as high as 4.5 V was obtained even when the gate length (Lg) was as small as 117 nm. It was also experimentally confirmed that the memory window increases with increasing gate voltage (Vg) in NOR-mode programming thanks to the increased efficiency of channel hot electron (CHE) injection. The developed tri-gate flash memory with improved IPD layer is useful for the further scaling of NOR-type flash memory.

[1]  Hiromi Yamauchi,et al.  Variability Analysis of TiN Metal-Gate FinFETs , 2010, IEEE Electron Device Letters.

[2]  Kenichi Ishii,et al.  Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography , 2003 .

[3]  K. Endo,et al.  Nanoscale Wet Etching of Physical-Vapor-Deposited Titanium Nitride and Its Application to Sub-30-nm-Gate-Length Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication , 2010 .

[4]  E. Suzuki,et al.  Cross-Sectional Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors , 2004 .

[5]  Experimental Study of Physical-Vapor-Deposited Titanium Nitride Gate with An n+-Polycrystalline Silicon Capping Layer and Its Application to 20 nm Fin-Type Double-Gate Metal?Oxide?Semiconductor Field-Effect Transistors , 2011 .

[6]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[7]  E. Suzuki,et al.  A Comparative Study of Nitrogen Gas Flow Ratio Dependence on the Electrical Characteristics of Sputtered Titanium Nitride Gate Bulk Planar Metal–Oxide–Semiconductor Field-Effect Transistors and Fin-Type Metal–Oxide–Semiconductor Field-Effect Transistors , 2009 .

[8]  K. Endo,et al.  Investigation of Low-Energy Tilted Ion Implantation for Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Extension Doping , 2010 .

[9]  E. Suzuki,et al.  Demonstration, analysis, and device design considerations for independent DG MOSFETs , 2005, IEEE Transactions on Electron Devices.

[10]  M. Masahara,et al.  Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching , 2003, IEEE Electron Device Letters.