A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

In this paper, we present a 39.1-to-41.6 GHz 1.2 V 64 mW DeltaSigma fractional-N frequency synthesizer that is implemented in 90nm CMOS. To reduce power consumption, a divide-by-4 injection-locking frequency divider (ILFD) is used in the feedback loop and a digital calibration technique is implemented to overcome the ILFD locking-range limitations.

[1]  Jri Lee.  A 75-GHz PLL in 90-nm CMOS Technology , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Ashoke Ravi,et al.  8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3/sup rd/ order, 3/5-bit IIR and 3/sup rd/ order 3-bit-FIR noise shapers in 90nm CMOS , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[3]  Yanping Ding,et al.  A 50-GHz Phase-Locked Loop in 0.13-$\mu$ m CMOS , 2007, IEEE Journal of Solid-State Circuits.

[4]  Shen-Iuan Liu,et al.  A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- $\mu$m CMOS Technology , 2007, IEEE Journal of Solid-State Circuits.

[5]  Shen-Iuan Liu,et al.  A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Carlo Samori,et al.  A 15-GHz broad-band ÷2 frequency divider in 0.13-μm CMOS for quadrature generation , 2005 .