A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization

This paper introduces MDAC equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain and settling errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240mW 2.1GS/s 12b ping-pong pipeline ADC in 40nm CMOS where MDAC RA power is reduced from 175mW to 53mW by 70%.

[1]  Greg Patterson,et al.  A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  Charles K. Sestok,et al.  A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC , 2011, 2011 IEEE International Solid-State Circuits Conference.

[3]  Jingbo Wang,et al.  A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[4]  Chun-Ying Chen,et al.  A 12b 3GS/s pipeline ADC with 500mW and 0.4 mm2 in 40nm digital CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[5]  Claudio Nani,et al.  A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist , 2011, 2011 IEEE International Solid-State Circuits Conference.

[6]  Claudio Nani,et al.  A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[7]  Ian Galton,et al.  A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  Pier Andrea Francese,et al.  A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency , 2009, IEEE Journal of Solid-State Circuits.

[9]  Pier Andrea Francese,et al.  A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[11]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..