A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing Extraction for Wearable Cardiovascular Monitoring

An ASIC for wearable cardiovascular monitoring is implemented using a topology that takes advantage of the electrocardiogram's (ECG) waveform to replace the traditional ECG instrumentation amplifier, ADC, and signal processor with a single chip solution. The ASIC can extract heartbeat timings in the presence of baseline drift, muscle artifact, and signal clipping. The circuit can operate with ECGs ranging from the chest location to remote locations where the ECG magnitude is as low as 30 μV. Besides heartbeat detection, a midpoint estimation method can accurately extract the ECG R-wave timing, enabling the calculations of heart rate variability. With 58 nW of power consumption at 0.8 V supply voltage and 0.76 mm 2 of active die area in standard 0.18 μm CMOS technology, the ECG ASIC is sufficiently low power and compact to be suitable for long term and wearable cardiovascular monitoring applications under stringent battery and size constraints.

[1]  Reid R. Harrison,et al.  A low-power, low-noise CMOS amplifier for neural recording applications , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[2]  David Blaauw,et al.  24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[3]  Rahul Wadke,et al.  Atrial fibrillation. , 2022, Disease-a-month : DM.

[4]  Refet Firat Yazicioglu,et al.  A 30µW Analog Signal Processor ASIC for biomedical signal monitoring , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[5]  Scott K. Arfin,et al.  Fast startup CMOS current references , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[6]  Daehwa Paik,et al.  A low-noise self-calibrating dynamic comparator for high-speed ADCs , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[7]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[8]  C. Sodini,et al.  The ear as a location for wearable vital signs monitoring , 2010, 2010 Annual International Conference of the IEEE Engineering in Medicine and Biology.

[9]  Alan B. Grebene,et al.  Analog Integrated Circuit Design , 1978 .

[10]  李永军,et al.  Atrial Fibrillation , 1999 .

[11]  Stuart N. Wooters,et al.  A 2.6-µW sub-threshold mixed-signal ECG SoC , 2009, 2009 Symposium on VLSI Circuits.

[12]  J. Waktare,et al.  ATRIAL fibrillation. , 2002, The Heart bulletin.

[13]  Naveen Verma,et al.  A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System , 2010, IEEE Journal of Solid-State Circuits.

[14]  Giovanni Calcagnini,et al.  On the resolution of ECG acquisition systems for the reliable analysis of the P-wave , 2012, Physiological measurement.

[15]  A. Khera,et al.  Forecasting the Future of Cardiovascular Disease in the United States: A Policy Statement From the American Heart Association , 2011, Circulation.

[16]  Denis C. Daly,et al.  A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy , 2009, IEEE Journal of Solid-State Circuits.

[17]  Jo Woon Chong,et al.  Arrhythmia Discrimination Using a Smart Phone , 2013, IEEE Journal of Biomedical and Health Informatics.