Fault Modeling and Testing of Flash Memories

Flash memories more and more occurs in complex integrated circuits designed for portable electronic devices and dominate the area of such circuits. The lack of defects within these memories is therefore one the key elements of the production yield for manufacturers of these types of applications. However, the high integration density and the complexity of the fabrication process make these Flash memories more and more prone to manufacturing defects. To exhibit the failures that affect the functionality of these memories, efficient and low cost test solutions must be proposed. The solutions and algorithms currently used to test RAM memories are not well adapted to test Flash memories due of the low programming time of such memories. Moreover, functional fault models proposed in the RAM testing literature are not always realistic in the case of Flash memories. The first part of this thesis proposes a complete analysis of actual defects extracted from silicon data extracted from a 150nm Flash technology. This analysis, based on a defect injection in a reduced Flash memory array, has allowed to exhibit a lot of faulty behaviors and to propose comprehensive fault models for all defects. The next part of this thesis focuses on the development of new and improved test solutions. The proposed solutions are based on Flash specificities like its concurrent programming mode allowing to program certain memory cell blocks in one time with the same pattern and with a reduced programming time. The evaluation of the proposed solutions is carried out with the help of a home made fault simulator. This evaluation has shown the efficiency of the proposed test solutions in terms of fault coverage and test time. The validation on a 4Mbits Flash memory has shown a considerable reduction in test time (by a factor of 34) as well as an improved fault coverage (especially for coupling faults) with respect to solutions currently used in industry.

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