SEERAD: A high speed yet energy-efficient rounding-based approximate divider

In this paper, a high speed yet energy-efficient approximate divider for error resilient applications is proposed. For the division operation, the divisor is rounded to a value with a specific form resulting in the transformation of the division operation to the multiplication one. The proposed approximate divider enjoys the flexibility of increasing the accuracy at the price of higher delay and hardware usage. The efficacy of the proposed approximate divider is evaluated in comparison to three different implementations of the SRT divider. The results show that the delay and energy consumption of the proposed approximate divider are, on average, 14 and 300 times smaller than those of the Radix-2 SRT with the carry-save reminder computation. Additionally, the effectiveness of the proposed approximate divider is studied in an image division operation performed in image processing applications. The results suggest the appropriateness of the proposed approximate divider for digital signal processing applications.

[1]  Wei Liu,et al.  Power Efficient Division and Square Root Unit , 2012, IEEE Transactions on Computers.

[2]  Tomás Lang,et al.  Digit-recurrence dividers with reduced logical depth , 2005, IEEE Transactions on Computers.

[3]  Fabrizio Lombardi,et al.  Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing , 2015, ACM Great Lakes Symposium on VLSI.

[4]  Subhasish Mitra,et al.  ERSA: Error Resilient System Architecture for probabilistic applications , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[5]  Kaushik Roy,et al.  IMPACT: IMPrecise adders for low-power approximate computing , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[6]  Luis Ceze,et al.  Architecture support for disciplined approximate programming , 2012, ASPLOS XVII.

[7]  . N.Venkateswaran,et al.  A Numerically Approximate High-speed Divider for Image Processing Applications , 2006 .

[8]  C. H. Chen,et al.  Digital Image Processing: An Algorithmic Approach with MATLAB , 2009 .

[9]  G. Bioul,et al.  Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems , 2006 .

[10]  Fabrizio Lombardi,et al.  A low-power, high-performance approximate multiplier with configurable partial error recovery , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Kia Bazargan,et al.  Axilog: Language support for approximate hardware design , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).