Virtual characterization for exhaustive DFM evaluation of logic cell libraries

Local layout effects create pattern dependencies at the 16nm node and below that make prediction of functional and parametric yield increasingly challenging. For logic design, precharacterizing all possible neighboring patterns is impractical due to exponential complexity, and silicon characterization is practically impossible. In this paper we propose a virtual characterization vehicle (VCV) methodology that can exhaustively identify all unique occurring layout patterns as a function of a radius of influence. VCVs compile the pattern frequency and enable exposure of hotspot patterns created by cell abutment. The VCV results can be used to guide the design and selection of cell library patterns and composition based on the corresponding impact on DFM metrics. Our results are demonstrated on a 14nm commercial cell library and results show how DFM quality can be improved with minimal impact on performance.