Seu and Sefi error detection and correction on a ddr3 memory system

Abstract This paper presents an embedded design that performs a novel Single Event Upset (SEU) and Single Event Functional Interrupt (SEFI) detection and recovery technique for DDR3 Synchronous Dynamic Random-Memories (SDRAM) memories in space applications. Using a memory system composed of four devices, this SEFI recovery method allows to restore the content of one entire device using the data and the Error Correction Code (ECC) bits stored in the other three devices. This design is implemented on a Xilinx Zynq-7000 System on Chip (SoC). The SEU detection and the recovery functionality is implemented on a Xilinx Zynq as an AXI bus peripheral. This peripheral is connected with the Processing System (PS) of the device via AXI bus, where a SEFI detection algorithm is implemented in a software application that runs in the ARM Cortex-A9. The developed technique also allows to inject errors to test the whole functionality.

[1]  Florent Miller,et al.  SDRAM Architecture & Single Event Effects Revealed with Laser , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[2]  P. Reviriego,et al.  SEU and SEFI Protection for DDR3 Memories in a Xilinx Zynq-7000 FPGA , 2017, 2017 6th International Conference on Space Mission Challenges for Information Technology (SMC-IT).

[3]  Veronique Ferlet-Cavrois,et al.  Heavy ion SEE test of 2 Gbit DDR3 SDRAM , 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

[4]  S.M. Guertin,et al.  Dynamic SDRAM SEFI detection and recovery test results , 2004, 2004 IEEE Radiation Effects Data Workshop (IEEE Cat. No.04TH8774).

[5]  D. C. Bossen,et al.  Orthogonal latin square codes , 1970 .

[6]  Yao Zhang,et al.  Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip , 2017, Microelectron. Reliab..

[7]  Shi-Jie Wen,et al.  Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams , 2015, 2015 IEEE International Reliability Physics Symposium.

[8]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[9]  R. Koga,et al.  Single Event Effects Sensitivity of DDR3 SDRAMs to Protons and Heavy Ions , 2012, 2012 IEEE Radiation Effects Data Workshop.

[10]  Veronique Ferlet-Cavrois,et al.  New SEE and TID test results for 2-Gbit and 4-Gbit DDR3 SDRAM devices , 2013, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

[11]  D. J. Sheldon,et al.  Programmatic Impact of SDRAM SEFI , 2012, 2012 IEEE Radiation Effects Data Workshop.

[12]  Pedro Reviriego,et al.  Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  F. Miller,et al.  Use of Laser to Explain Heavy Ion Induced SEFIs in SDRAMs , 2010, IEEE Transactions on Nuclear Science.

[14]  Steven M. Guertin.  Analysis of SDRAM SEFIs , 2012 .

[15]  Martin Herrmann,et al.  In-Situ TID Test of 4-Gbit DDR3 SDRAM Devices , 2013, 2013 IEEE Radiation Effects Data Workshop (REDW).

[16]  Salvatore Pontarelli,et al.  Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Shu Lin,et al.  Error Control Coding , 2004 .