论文信息 - 1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links

1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links

Design and simulation of a low power consuming MMIC chip set is presented in this paper, which is used as an optical receiver and clock recovery circuit operating up to 1.25 Gb/s. This design is based on BTA24 Si BJT transistor array from Bipolarics. Major design innovations such as push-pull self-oscillating mixer and a push-push frequency doubler is used to provide a total power consumption of 247 mW in an area of only 700 /spl mu/m/spl times/700 /spl mu/m.

Afshin S. Daryoush | X. Zhang | J. Y. Lin

[1] A.S. Daryoush,et al. Design of clock recovery MMIC using large-signal computer-aided analysis , 1995, Proceedings of 1995 IEEE MTT-S International Microwave Symposium.

[2] Afshin S. Daryoush,et al. An efficient self-oscillating mixer for communications , 1994 .

[3] P. O'Connor,et al. A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC , 1991 .

[4] R. Paski,et al. A regenerator chip set for high speed digital transmission , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5] Hans-Martin Rein. Multi-gigabit-per-second silicon bipolar ICs for future optical-fiber transmission systems , 1988 .

[6] U. Langmann,et al. A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s , 1992 .