High defect tolerant low cost memory chips

Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundancy in memory designs driven by the fabrication cost and the yield. It also proposes a new memory architecture that fills the gap between the existing all-or-none extremes with memories. Experiments show that the new scheme reduces cost by up to 70%.

[1]  Fabrizio Lombardi,et al.  New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  W. Kent Fuchs,et al.  Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.

[3]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[4]  Masashi Horiguchi,et al.  A flexible redundancy technique for high-density DRAMs , 1991 .

[5]  Shyue-Kung Lu,et al.  Built-in self-test and repair (BISTR) techniques for embedded RAMs , 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

[6]  Pinaki Mazumder,et al.  A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Jin-Young Park,et al.  A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[10]  John Day.  A Fault-Driven, Comprehensive Redundancy Algorithm , 1985, IEEE Design & Test of Computers.

[11]  Dilip K. Bhavsar.  An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264 , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).