Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

[1]  Deog-Kyoon Jeong,et al.  A 0.4-to-1 V Voltage Scalable $\Delta \Sigma $ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Michiel Steyaert,et al.  A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[3]  Fabian Khateb,et al.  A 0.3-V 98-dB Rail-to-Rail OTA in $0.18~\mu$ m CMOS , 2020, IEEE Access.

[4]  J.H. Huijsing,et al.  A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz $1/f$ Noise Corner and an AC-Coupled Ripple Reduction Loop , 2009, IEEE Journal of Solid-State Circuits.

[5]  Franco Maloberti,et al.  A 170.7-dB FoM-DR 0.45/0.6-V Inverter-Based Continuous-Time Sigma–Delta Modulator , 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Ali Esmailiyan,et al.  A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Edgar Sanchez-Sinencio,et al.  Power-Scaling Output-Compensated Three-Stage OTAs for Wide Load Range Applications , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Kent Layton,et al.  A 0.2-V 10-bit 5-kHz SAR ADC with Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator , 2020, 2020 IEEE Custom Integrated Circuits Conference (CICC).

[9]  Yi-Chun Shih,et al.  An Inductorless DC–DC Converter for Energy Harvesting With a 1.2-$ \mu\hbox{W}$ Bandgap-Referenced Output Controller , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Yong Lian,et al.  A 61-nW Level-Crossing ADC With Adaptive Sampling for Biomedical Applications , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  P. Bruschi,et al.  A Two-Stage Switched-Capacitor Integrator for High Gain Inverter-Like Architectures , 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Jean-Baptiste Begueret,et al.  A design-oriented approach for modeling integrators non-idealities in discrete-time sigma-delta modulators , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[13]  Van-Duong Dao.  An experimental exploration of generating electricity from nature-inspired hierarchical evaporator: The role of electrode materials. , 2020, The Science of the total environment.

[14]  Liyuan Liu,et al.  A Discrete-Time Audio $\Delta\Sigma$ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques , 2020, IEEE Journal of Solid-State Circuits.

[15]  Yan Han,et al.  A 0.8-V 230-$\mu$ W 98-dB DR Inverter-Based $\Sigma \Delta$ Modulator for Audio Applications , 2013, IEEE Journal of Solid-State Circuits.

[16]  Massimo Piotto,et al.  A 2 nW 0.25 V 140 dB-FOM Inverter-Based First Order ΔΣ Modulator , 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  C. Rodrigues,et al.  Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors , 2020, Electronics.

[18]  George Suárez,et al.  Behavioral Modeling Methods for Switched-Capacitor $\Sigma \Delta$ Modulators , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Maryam Shojaei Baghini,et al.  A 300-mV Auto Shutdown Comparator-Based Continuous Time Δ∑ Modulator , 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Sheng Xu,et al.  Soft, stretchable, high power density electronic skin-based biofuel cells for scavenging energy from human sweat , 2017 .

[21]  Andrea Baschirotto,et al.  Modeling sigma-delta modulator non-idealities in SIMULINK(R) , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[22]  Fabian Khateb,et al.  A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18- $\mu$ m CMOS , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Massimo Alioto,et al.  Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation , 2020, IEEE Access.

[24]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[25]  Belén Pérez-Verdú,et al.  CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom , 2006 .

[26]  Gabor C. Temes,et al.  Incremental Delta-Sigma ADCs: A Tutorial Review , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Kenneth R. Laker,et al.  Parasitic compensated switched capacitor circuits , 1981 .

[28]  Massimo Piotto,et al.  A 0.3 V 15 nW 69 dB SNDR Inverter-Based Δ∑ Modulator in 0.18 μm CMOS , 2019, 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME).

[29]  Nobutaka Kuroki,et al.  A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting , 2020, 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS).

[30]  Joseph Wang,et al.  A 0.3-V CMOS Biofuel-Cell-Powered Wireless Glucose/Lactate Biosensing System , 2018, IEEE Journal of Solid-State Circuits.

[31]  Massimo Alioto,et al.  Enabling the Internet of Things: From Integrated Circuits to Integrated Systems , 2017 .

[32]  Deog-Kyoon Jeong,et al.  A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors , 2019, IEEE Access.

[33]  R.W. Dutton,et al.  Impact of Scaling on Analog Performance and Associated Modeling Needs , 2006, IEEE Transactions on Electron Devices.

[34]  Montree Kumngern,et al.  0.3-V Nanopower Biopotential Low-Pass Filter , 2020, IEEE Access.

[35]  Van-Duong Dao,et al.  Recent advances and challenges for water evaporation-induced electricity toward applications , 2021, Nano Energy.

[36]  Massimo Piotto,et al.  Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop , 2020, Electronics.

[37]  Sameer R. Sonkusale,et al.  A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[38]  Razvan G. Vieru,et al.  Inverter-based ultra low voltage differential amplifiers , 2011, CAS 2011 Proceedings (2011 International Semiconductor Conference).

[39]  Boris Murmann,et al.  A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI , 2017, IEEE Journal of Solid-State Circuits.

[40]  Gabor C. Temes,et al.  Switched-capacitor integrators with low finite-gain sensitivity , 1985 .

[41]  Bram Nauta,et al.  A CMOS transconductance-C filter technique for very high frequencies , 1992 .

[42]  Philip K. T. Mok,et al.  5.11 A 65nm inverter-based low-dropout regulator with rail-to-rail regulation and over −20dB PSR at 0.2V lowest supply voltage , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[43]  Ali Fazli Yeknami.  A 300-mV ΔΣ Modulator Using a Gain-Enhanced, Inverter-Based Amplifier for Medical Implant Devices , 2016 .

[44]  Massimo Piotto,et al.  Analysis and Simulation of Chopper Stabilization Techniques Applied to Delta-Sigma Converters , 2018, 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[45]  Qiang Li,et al.  Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators , 2019, IEEE Journal of Solid-State Circuits.