Energy efficient computing by multi-mode addition

Abstract While adders are usually designed for the worst-case where their carry propagates through the entire bits, those cases rarely happen at real operation. This work takes advantage of the infrequent worst-case occurrences by designing adders for the average-case. Such design implies that computation errors may happen. Those are being corrected by implementing multi-mode addition with the aid of a dedicated control circuit. A power-delay-energy model is presented, enabling to find the optimal design point. We show that for cases where the system׳s critical paths are dictated by the adders, the system׳s operation voltage can be scaled, without harming the clock cycle and with very small performance degradation. For an adder per-se, potential energy savings of up to 50% is shown. The multi-mode adder has been integrated in a 32-bit pipelined MIPS processor, validating the correctness of such design approach.

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