VIA design rule consideration in multi-layer maze routing algorithms

Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integra- tion, printed circuit board and multichip modules In this paper, we show that finding an optimal route of a two-pin net in a mul- tilayer routing environment under practical via design rules can be surprisingly difficult. A straightforward extension to the maze routing algorithm that disallows via-rule incorrect routes may ei- ther cause a suboptimal route to be found, or more seriously, cause the failure to find any route even if one exists. We present a refined heuristic to this problem by embedding the distance to the most re- cently placed via in an extended connection graph so that the maze routing algorithm has a higher chance of finding a via-rule cor- rect optimum path in the extended connection graph. We further present efficient data-structures to implement the maze routing al- gorithm without the need to preconstruct the extended connection graph. Experimental results confirmed the usefulness of our algo- rithm and its applicability to a wide range of CMOS technologies.