Design on ESD protection scheme for IC with power-down-mode operation

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-/spl mu/m silicided CMOS process.

[1]  R. N. Rountree,et al.  Internal chip ESD phenomena beyond the protection circuit , 1988 .

[2]  Ming-Dou Ker,et al.  ESD protection design for IC with power-down-mode operation , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[3]  C. Duvvury,et al.  A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[4]  E. Worley,et al.  Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[5]  Satoshi Shigematsu,et al.  A 1-V high-speed MTCMOS circuit scheme for power-down application circuits , 1997, IEEE J. Solid State Circuits.

[6]  M.-D. Ker.  Area-efficient VDD-to-vSS ESD Clamp Circuit By Using Substrate-triggering Field-oxide Device (STFFOD) For Whole-chip ESD Protection , 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

[7]  M. Ker.  Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .

[8]  C. Duvvury,et al.  A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 /spl mu/m CMOS I/O application , 2002, Digest. International Electron Devices Meeting,.

[9]  E. C. Dijkmans,et al.  A 3/5 V compatible I/O buffer , 1995 .

[10]  Timothy J. Maloney,et al.  Basic ESD and I/O Design , 1998 .