Reducing Power Dissipation in the Sublithographic Crossbar Architecture

Contemporary nanotechnology has brought ultra-high device densities within reach. Along with reliability issues, one of the greatest problems impeding further progress in achieving ever-higher densities is that of power dissipation. The ability to construct layers of crossbar arrays of Si nanowires and routing in 3 dimensions exists, but the energy dissipated using conventional CMOS circuit design techniques is unmanageable without the large surface area relied upon in the past to siphon the heat away. In this paper we explore applying existing adiabatic computation techniques to nanoscale computing to determine the feasibility, tradeoffs, and overhead of such an implementation. In addition, we examine possible construction methods for implementing nano-scale inductors for the purposes of realizing appropriate rail drivers for the adiabatic logic schemes.