A 5-Gbps FPGA prototype of a (31,29)2 Reed-Solomon turbo decoder

In this paper, the use of single-error-correcting Reed-Solomon (RS) product codes are investigated in an ultra high-speed context. A full-parallel architecture dedicated to the turbo decoding process of RS product codes is described. An experimental setup composed of a Dinigroup board that includes six Xilinx Virtex-5 LX330 FPGAs is employed. Thus, a full-parallel turbo decoding architecture dedicated to the (31, 29)2 RS product code has been designed and then implemented into a 5 Gbps experimental setup. The purpose of this prototype is to demonstrate that RS turbo decoders can effectively achieve information rates above 1 Gbps. The results show that the RS turbo product codes offer a good complexity/performance trade off for ultra-high throughputs. The major limitation in terms of data rate of our prototype is the data exchange between the FPGAs of the board. Indeed, the turbo decoder architecture enables decoding at information rates until 10 Gbps onto FPGA devices.

[1]  R. Pyndiah,et al.  Reliable transmission with low complexity Reed-Solomon block turbo codes , 2004, 1st International Symposium onWireless Communication Systems, 2004..

[2]  R. Pyndiah,et al.  Block turbo codes: ten years later , 2004 .

[3]  Christophe Jégo,et al.  Towards Gb/s turbo decoding of product code onto an FPGA device , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[4]  Keshab K. Parhi,et al.  High speed VLSI architecture design for block turbo decoder , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[6]  Christophe Jégo,et al.  Efficient architecture for Reed Solomon block turbo code , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[7]  David Chase,et al.  Class of algorithms for decoding block codes with channel measurement information , 1972, IEEE Trans. Inf. Theory.

[8]  Camille Leroux,et al.  Full-parallel architecture for turbo decoding of product codes , 2006 .

[9]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[10]  Ramesh Pyndiah,et al.  Performance of Reed-Solomon block turbo code , 1996, Proceedings of GLOBECOM'96. 1996 IEEE Global Telecommunications Conference.

[11]  Ramesh Pyndiah,et al.  Some Results on the Binary Minimum Distance of Reed-Solomon Codes and Block Turbo Codes , 2007, 2007 IEEE International Conference on Communications.

[12]  Ramesh Pyndiah,et al.  New architecture for high data rate turbo decoding of product codes , 2002, Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.

[13]  Ramesh Pyndiah,et al.  Near optimum decoding of product codes , 1994, 1994 IEEE GLOBECOM. Communications: The Global Bridge.

[14]  Jean-Luc Danger,et al.  Efficient FPGA implementation of Gaussian noise generator for communication channel emulation , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[15]  Frank R. Kschischang,et al.  A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[16]  Takashi Mizuochi,et al.  Experimental demonstration of net coding gain of 10.1 dB using 12.4 Gb/s block turbo code with 3-bit soft decision , 2003, OFC 2003 Optical Fiber Communications Conference, 2003..

[17]  Ramesh Pyndiah,et al.  Performance and complexity of block turbo decoder circuits , 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

[18]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.