The noise margins for CMOS SRAM cells composed of scaled-down MOSFETs are described.
First, an analytical method estimating the noise margins for the CMOS memory cells is proposed. Then scaled-down MOSFET effects, i.e., the mobility degradation and the parasitic resistances will be considered. How each of these effects changes the noise margins will be studied using analytical equations. As a result, it will be determined that the mobility degradation worsens the read margin by considerably reducing the CMOS inverter logic threshold voltage. It will also be determined that the parasitic resistances associated with the drive transistors degrade the read margin.
Finally, equations are derived for the threshold voltage and cell ratio for a given noise margin. Its effectiveness will be demonstrated for 0.2 μm CMOS memory cells.
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