Single event upset resistant synchronously resettable D flip-flop

The invention discloses a single event upset resistant synchronously resettable D flip-flop, aiming at improving the single event upset resistance of a resettable D flip-flop. The D flip-flop is composed of a clock circuit, a master latch, a slave latch, a first inverter circuit and a second inverter circuit, wherein the master latch is composed of 12 PMOS (P-channel Metal Oxide Semiconductor) FETs (Field Effect Transistors) and 12 NMOS (N-channel Metal Oxide Semiconductor) FETs, the slave latch is composed of 10 PMOS FETs and 10 NMOS FETs, duplication redundant reinforcement is performed on the master latch and the slave latch, and the C2MOS (Clocked Complementary Metal Oxide Semiconductor) circuit structures of the master latch and the slave latch are improved, i.e. a pull-up circuit and a pull-down circuit in the mutually redundant C2MOS circuits are separated from the master latch, and a pull-up PMOS FET and a pull-down NMOS FET in the mutually redundant C2MOS circuits are separated from the slave latch. The single event upset resistant resettable D flip-flop disclosed by the invention has strong single event upset resistance, is suitable for a standard cell library of a single event upset resistance reinforced integrated circuit, and is applied to the fields of aviation, aerospace and the like.