Direct fabrication of integrated 3D Au nanobox arrays by sidewall deposition with controllable heights and thicknesses

This paper provides a unique strategy for controlling integrated hollow nanostructure arrays such as boxes or pillars at the nanometer scale. The key merit of this technique is that it can overcome resolution limits by sidewall deposition and deposit various materials using a sputtering method. The sputtering method can be replaced by other dry deposition techniques such as pulsed laser deposition (PLD) for complex functional materials. Furthermore, it can produce low-cost large-area fabrication and high reproducibility using the NIL (nanoimprint lithograph) process. The fabrication method consists of a sequence of bilayer spin-coating, UV-NIL, RIE (reactive ion etching), sputtering, ion milling and piranha cleaning processes. By changing the deposition time and molds, various thicknesses and shapes can be fabricated, respectively. Furthermore, the fabricated Au box nanostructure has a bending zone of the top layer and a ∼17 nm undercut of the bottom layer as observed by SEM (scanning electron microscope). The sidewall thickness was changed from 12 to 61 nm by controlling the deposition time, and was investigated to understand the relationship with blanket thicknesses and geometric effects. The calculated sidewall thickness matched well with experimental results. Using smaller hole-patterned molds, integrated nanobox arrays, with inner squares measuring ∼160 nm, and nanopillar arrays, with inside pores measuring ∼65 nm, were fabricated under the same conditions.

[1]  Hongyuan Wei,et al.  Nanoring magnetic tunnel junction and its application in magnetic random access memory demo devices with spin-polarized current switching (invited) , 2008 .

[2]  M. Hara,et al.  Detection of paired domain walls in a ferromagnetic ring by a bend resistance measurement , 2008 .

[3]  Y. Yao,et al.  Determining vortex chirality in ferromagnetic ring by lateral nonlocal spin valve , 2008 .

[4]  Xiaogan Liang,et al.  Single sub-20 nm wide, centimeter-long nanofluidic channel fabricated by novel nanoimprint mold fabrication and direct imprinting. , 2007, Nano letters.

[5]  A. Fert,et al.  The emergence of spin electronics in data storage. , 2007, Nature materials.

[6]  Hongyuan Wei,et al.  Patterned nanoring magnetic tunnel junctions , 2007 .

[7]  Mathias Rommel,et al.  UV nanoimprint materials: Surface energies, residual layers, and imprint quality , 2007 .

[8]  Ye Cai,et al.  Chemical reduction of three-dimensional silica micro-assemblies into microporous silicon replicas , 2007, Nature.

[9]  Steven C. Currall,et al.  What drives public acceptance of nanotechnology? , 2006, Nature nanotechnology.

[10]  K. Jensen,et al.  Cells on chips , 2006, Nature.

[11]  Qiguang Li,et al.  Photoconductive cadmium sulfide hemicylindrical shell nanowire ensembles. , 2005, Nano letters.

[12]  J. Eijkel,et al.  Technologies for nanofluidic systems: top-down vs. bottom-up--a review. , 2005, Lab on a chip.

[13]  Andrew A. Bettiol,et al.  Fabrication of high aspect ratio 100nm metallic stamps for nanoimprint lithography using proton beam writing , 2004 .

[14]  Wei Wu,et al.  Fabrication of 5 nm linewidth and 14 nm pitch features by nanoimprint lithography , 2004 .

[15]  Steven G. Johnson,et al.  A three-dimensional optical photonic crystal with designed point defects , 2004, Nature.

[16]  John A. Rogers,et al.  Three-Dimensional and Multilayer Nanostructures Formed by Nanotransfer Printing , 2003 .

[17]  Henry I. Smith,et al.  Metastable states in magnetic nanorings , 2003 .

[18]  Jeffrey Bokor,et al.  Fabrication of Sub-10-nm Silicon Nanowire Arrays by Size Reduction Lithography , 2003 .

[19]  H. Ryssel,et al.  Simulation of the influence of via sidewall tapering on step coverage of sputter-deposited barrier layers , 2002 .

[20]  C. Hu,et al.  Nanoscale CMOS spacer FinFET for the terabit era , 2002 .

[21]  Lloyd R. Harriott,et al.  Limits of lithography , 2001, Proc. IEEE.

[22]  Shinji Matsui,et al.  Three-dimensional nanostructure fabrication by focused-Ion-beam chemical vapor deposition , 2000, TRANSDUCERS '03. 12th International Conference on Solid-State Sensors, Actuators and Microsystems. Digest of Technical Papers (Cat. No.03TH8664).

[23]  Christophe Vieu,et al.  Electron beam lithography: resolution limits and applications , 2000 .

[24]  Wei Zhang,et al.  Sub-10 nm imprint lithography and applications , 1997, 1997 55th Annual Device Research Conference Digest.

[25]  Stephen Y. Chou,et al.  Imprint of sub-25 nm vias and trenches in polymers , 1995 .

[26]  David S. Y. Hsu,et al.  20 nm linewidth platinum pattern fabrication using conformal effusive‐source molecular precursor deposition and sidewall lithography , 1992 .

[27]  Run‐Wei Li,et al.  Nanopatterning of perovskite manganite thin films by atomic force microscope lithography , 2004 .

[28]  G. Whitesides,et al.  Soft lithographic methods for nano-fabrication , 1997 .

[29]  Yonggang Huang,et al.  References and Notes Supporting Online Material Materials and Methods Som Text Figs. S1 and S2 References Stretchable and Foldable Silicon Integrated Circuits , 2022 .