The complementary field-effect transistor (CFET) with stacked N-type FET (NFET) and P-type FET (PFET) is an attractive approach to shrink the footprint of multiple devices at circuit level and increase transistor density. Compared with traditional device structure, the unique geometry of CFET brings very different parasitics. In this work, we take the inverter as an exemplar CFET circuit building block and provide analytical compact models of calculating parasitic capacitance, which is critical to enable fast and accurate simulations at circuit level. The validity of the models is calibrated and verified with 3-D numerical simulations. A comparison between the CFET inverter with its same ground-rule gate-all-around FET (GAAFET) counterpart reveals the critical CFET design parameters and demonstrates performance advantage of CFET architecture.