Decimal Division Using the Newton–Raphson Method and Radix-1000 Arithmetic

Computer arithmetic is predominantly performed using binary arithmetic because the hardware implementations of the operations are simpler than those for decimal computation. However, many decimal fractions cannot be represented exactly as binary fractions with a finite number of bits.

[1]  Tomás Lang,et al.  A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture , 2007, IEEE Transactions on Computers.

[2]  M. Cowlishaw Densely packed decimal encoding , 2002 .

[3]  Jean-Pierre Deschamps,et al.  FPGA Implementations of BCD Multipliers , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[4]  Michael J. Schulte,et al.  Decimal multiplication via carry-save addition , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[5]  Paolo Montuschi,et al.  A New Family of High.Performance Parallel Decimal Multipliers , 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

[6]  Siegfried M. Rump,et al.  Accurate Floating-Point Summation Part I: Faithful Rounding , 2008, SIAM J. Sci. Comput..

[7]  Jean-Pierre Deschamps,et al.  Decimal division: Algorithms and FPGA implementations , 2010, 2010 VI Southern Programmable Logic Conference (SPL).

[8]  Mário P. Véstias,et al.  Decimal multiplier on FPGA using embedded binary multipliers , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[9]  A. Nannarelli,et al.  A Radix-10 Combinational Multiplier , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[10]  Paolo Montuschi,et al.  A radix-10 SRT divider based on alternative BCD codings , 2007, 2007 25th International Conference on Computer Design.

[11]  Michael J. Schulte,et al.  Decimal floating-point division using Newton-Raphson iteration , 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

[12]  Michael F. Cowlishaw,et al.  Decimal floating-point: algorism for computers , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[13]  Braden Phillips,et al.  Fast Decimal Floating-Point Division , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Michael J. Schulte,et al.  A high-frequency decimal multiplier , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[15]  Mário P Véstias,et al.  Parallel decimal multipliers using binary multipliers , 2010, 2010 VI Southern Programmable Logic Conference (SPL).

[16]  Jean-Michel Muller,et al.  Elementary Functions: Algorithms and Implementation , 1997 .

[17]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[18]  Mario P. Vestias,et al.  Iterative decimal multiplication using binary arithmetic , 2011, 2011 VII Southern Conference on Programmable Logic (SPL).

[19]  Jean-Michel Muller,et al.  Newton-Raphson algorithms for floating-point division using an FMA , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

[20]  T. J. Rivlin The Chebyshev polynomials , 1974 .

[21]  Luigi Dadda,et al.  A variant of a radix-10 combinational multiplier , 2008, 2008 IEEE International Symposium on Circuits and Systems.