Two-dimensional time-division multiplexing for 3D-SoCs

Through-silicon vias (TSVs) are used as high-speed interconnects between dies in a 3D System-on-Chip (SoC). However, their speed cannot be utilized during test application due to inherent limitations of the scan chains of the cores, which prevent the use of high shift frequencies. Moreover, due to their high area cost, only a limited number of TSVs can be used for test application. As a result, the time needed for transferring test data to the cores in multiple dies can be considerable. We propose an efficient test-access mechanism (TAM) architecture, which exploits the high speed of TSVs to minimize the time for testing 3D SoCs. By the means of time-division multiplexing and an effective test scheduling method, the proposed TAM architecture offers significant savings in test time, TSV count and TAM cost.

[1]  W. Press,et al.  Numerical Recipes: The Art of Scientific Computing , 1987 .

[2]  Erik Jan Marinissen,et al.  Optimization methods for post-bond die-internal/external testing in 3D stacked ICs , 2010, 2010 IEEE International Test Conference.

[3]  Erik Jan Marinissen,et al.  Robust Optimization of Test-Access Architectures Under Realistic Scenarios , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Erik Jan Marinissen,et al.  Optimization Methods for Post-Bond Testing of 3D Stacked ICs , 2012, J. Electron. Test..

[5]  Bernard Chazelle,et al.  The Bottomn-Left Bin-Packing Heuristic: An Efficient Implementation , 1983, IEEE Transactions on Computers.

[6]  Mitsumasa Koyanagi,et al.  Low-Resistance Cu-Sn Electroplated–Evaporated Microbumps for 3D Chip Stacking , 2012, Journal of Electronic Materials.

[7]  Hafizur Rahaman,et al.  Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

[8]  Erik Jan Marinissen,et al.  Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base , 2011, 2011 IEEE International Test Conference.

[9]  Sung Kyu Lim,et al.  Slew-aware buffer insertion for through-silicon-via-based 3D ICs , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[10]  Erik Jan Marinissen,et al.  Test-architecture optimization for TSV-based 3D stacked ICs , 2010, 2010 15th IEEE European Test Symposium.

[11]  Cheng-Wen Wu,et al.  SOC Test Architecture and Method for 3-D ICs , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Yusuf Leblebici,et al.  Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs , 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

[13]  Erik Jan Marinissen,et al.  DfT Architecture for 3D-SICs with Multiple Towers , 2011, 2011 Sixteenth IEEE European Test Symposium.

[14]  Fangming Ye,et al.  TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[15]  H. Reichl,et al.  High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[16]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[17]  Yuan Xie,et al.  Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs , 2009, 2009 IEEE International Conference on Computer Design.

[18]  Erik Jan Marinissen,et al.  Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Hsien-Hsin S. Lee,et al.  Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[20]  Vivek Chickermane,et al.  Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers , 2013, 2013 18th IEEE European Test Symposium (ETS).

[21]  Qiang Xu,et al.  Test architecture design and optimization for three-dimensional SoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[22]  Charles H.-P. Wen,et al.  Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Yuan Xie,et al.  Design space exploration for 3D architectures , 2006, JETC.

[24]  Mario H. Konijnenburg,et al.  3D DfT architecture for pre-bond and post-bond testing , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

[25]  Ding-Ming Kwai,et al.  A Test Integration Methodology for 3D Integrated Circuits , 2010, 2010 19th IEEE Asian Test Symposium.

[26]  Krishnendu Chakrabarty,et al.  Time-Division Multiplexing for Testing DVFS-Based SoCs , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[28]  Xiaoxia Wu,et al.  Scan chain design for three-dimensional integrated circuits (3D ICs) , 2007, 2007 25th International Conference on Computer Design.

[29]  Frédéric Pétrot,et al.  Asynchronous 3D-NoCs Making Use of Serialized Vertical Links , 2011, 3D Integration for NoC-based SoC Architectures.