Chapter 15 INTERCONNECT AND MEMORY ORGANIZATION IN SOCS FOR ADVANCED SET-TOP BOXES AND TV Evolution, Analysis, and Trends

In this chapter we show that the organization of the communication and memory infrastructures is critical in today’s complex systems-on-chip (SOCs). We further show that resource management in the form of scheduling or arbitration is common to them both. The increasing importance of these issues is illustrated by following the evolution of an advanced set-top box and highdefinition digital TV application (ASTB) and its SOC implementations over time. In Section 2, we introduce the application domain (embedded systems for high-volume consumer electronics), and the application (advanced set-top boxes for high-definition digital and analog TV). The computation kernels and the communication (data rates, latencies) needed for real-time audio and video are demanding. Meeting real-time requirements, while minimizing resources for cost-effectiveness is challenging for such large heterogeneous SOCs. In Sections 4 to 6, we review two existing and one possible future SOC implementation of the ASTB application, along the following axes, introduced in detail in Section 3. We commence with the application itself, including real-time requirements, the computation kernels, the kinds of traffic flowing between them, and the logical memories used by them. The following axes categorize its implementation; the mapping of computation (types and number of IP blocks) and communication. Then we consider the interconnect organization, communication abstraction (how IP blocks interact with the interconnect),

[1]  Santanu Dutta,et al.  Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..

[2]  P. Klapproth.  General architectural concepts for IP core re-use , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[3]  André DeHon,et al.  Robust, High-Speed Network Design for Large-Scale Multiprocessing , 1993 .

[4]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Maik Brett,et al.  Video processing for single-chip DVB decoder , 2001, IEEE Trans. Consumer Electron..

[6]  Jochen A. G. Jess,et al.  Stream communication between real-time tasks in a high-performance multiprocessor , 1998, Proceedings Design, Automation and Test in Europe.

[7]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[8]  Yasoo Harada,et al.  Single chip video processor for digital HDTV , 2001, IEEE Trans. Consumer Electron..

[9]  Kees G. W. Goossens,et al.  Guaranteeing the Quality of Services in Networks on Chip , 2003, Networks on Chip.

[10]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[11]  Michael Redeker,et al.  A Large-Area Integrated Multiprocessor System for Video Applications , 2002, IEEE Des. Test Comput..

[12]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[13]  R. Kramer.  Consumer electronics as silicon engine , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[14]  Markus Schu,et al.  System-on-silicon solution for high quality consumer video processing-the next generation , 2001, IEEE Trans. Consumer Electron..

[15]  Alberto L. Sangiovanni-Vincentelli,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  de G Gerard Haan,et al.  Video processing for multimedia systems , 2000 .

[17]  Peter H. N. de With,et al.  A Flexible Heterogeneous Video Processor System For Television Applications. , 1998, International 1998 Conference on Consumer Electronics.

[18]  Gerard de Haan,et al.  IC for motion compensated de-interlacing, noise reduction, and picture rate conversion , 1999, 1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277).

[19]  Om Prakash Gangwal,et al.  Understanding video pixel processing applications for flexible implementations , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[20]  Drew Wingard,et al.  Socket-Based Design Using Decoupled Interconnects , 2005 .

[21]  Kees G. W. Goossens,et al.  Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[22]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).