A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips

With technology scaling, process variations influence the performance, power and reliability significantly, especially for multi-core and many-core systems. Faulty-tolerant multi-core architectures are paid widely attention to, which integrate redundant cores to improve the manufacturing yield. In this paper, a two-stage variation-aware task mapping scheme is proposed for multi-core NoCs with redundant cores. Firstly, a static genetic task mapping algorithm is presented to generate multiple task mapping solutions to cover a maximum range of chips. Then, at runtime, one optimal mapping solution is selected, and logical cores are mapped to physical available cores. Both core asymmetry and topology changes are considered in the proposed approach. Experimental results demonstrate that the proposed approach increases the performance yield by 56%, and the communication cost is reduced by 11.3%.