Performance and Power Consumption Trade-Off in UTBB FDSOI Inverters Operated at NTV for IoT Applications

Power consumption and I<sub>on</sub>/I<sub>off</sub> ratio of an ultra-thin body and buried oxide fully depleted silicon on insulator CMOS inverter circuit has been calculated at near-threshold voltage operation from TCAD simulations. TCAD outputs (current, voltage, and capacitance) were used as parameters to solve the inverter circuit. Besides, a bias operation point (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ OP}}$ </tex-math></inline-formula>) has been proposed, which provides a good trade-off between the I<sub>on</sub>/I<sub>off</sub> ratio and the energy consumption. Variations of this operation point, due to the presence of interface traps, have been also analyzed.

[1]  Vivek De.  Energy efficient computing in nanoscale CMOS: Challenges and opportunities , 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[2]  T. Hiramoto,et al.  Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme , 2007, IEEE Transactions on Electron Devices.

[3]  W. Fichtner,et al.  Quantum device-simulation with the density-gradient model on unstructured grids , 2001 .

[4]  Marco Lanuzza,et al.  Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design , 2014, 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI).

[5]  Y. Apanovich,et al.  Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  D. Flandre,et al.  Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures , 2015, 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro).

[7]  O. Rozeau,et al.  Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit , 2011, IEEE Transactions on Electron Devices.

[8]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[9]  Luca Benini,et al.  Towards near-threshold server processors , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  E. Simoen,et al.  Enhanced dynamic threshold voltage UTBB SOI nMOSFETs , 2015 .

[11]  Alexander Fish,et al.  Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[12]  S. Selberherr.  Analysis and simulation of semiconductor devices , 1984 .

[13]  Juin J. Liou,et al.  A review of recent MOSFET threshold voltage extraction methods , 2002, Microelectron. Reliab..

[14]  Trond Ytterdal,et al.  Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing , 2016, 2016 IEEE Nordic Circuits and Systems Conference (NORCAS).

[15]  Jan M. Rabaey,et al.  Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.

[16]  M. Porti,et al.  Efficient methodology to extract interface traps parameters for TCAD simulations , 2017 .

[17]  Bastien Giraud,et al.  Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[18]  Sébastien Haendler,et al.  Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs , 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

[19]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[20]  Mehdi Baradaran Tahoori,et al.  Test implications and challenges in near threshold computing special session , 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

[21]  FZ Rahou,et al.  Self- heating effects in SOI MOSFET transistor and numerical simulation using Silvaco software , 2012, 2012 24th International Conference on Microelectronics (ICM).