Co-design of ESD protection and LNA in RFIC

This paper introduces a new FoM (figure of merit) to evaluate the overall performance of ESD and LNA and presents a design procedure of establishing a standard library of ESD protection cells to reduce the design time and complexity for RFIC designer. The electrostatic discharge protection cells have been designed in a 0.35μm BiCMOS process. The ESD robustness and RF characteristics will be verified when the RF chip is done.