Supply and threshold voltage scaling for low power CMOS

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields.

[1]  Gu-Yeon Wei,et al.  A low power switching power supply for self-clocked systems , 1996, ISLPED '96.

[2]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[3]  A. Chandrakasan,et al.  SOIAS: dynamically variable threshold SOI with active substrate , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[4]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[5]  J. Burr,et al.  Ultra low power CMOS technology , 1991 .

[6]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[7]  J. Yamada,et al.  A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[8]  C. Piguet,et al.  A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  H. Hara,et al.  50% active-power saving without speed degradation using standby power reduction (SPR) circuit , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[10]  R.R. Troutman,et al.  VLSI limitations from drain-induced barrier lowering , 1979, IEEE Transactions on Electron Devices.

[11]  Bevan M. Baas,et al.  Stanford's ultra-low-power CMOS technology and applications , 1996 .

[12]  Ih-Chin Chen,et al.  A device design study of 0.25 /spl mu/m gate length CMOS for 1 V low power applications , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[13]  J. Burr,et al.  Cryogenic ultra low power CMOS , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[14]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[15]  Ih-Chin Chen,et al.  An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.