A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDes

This paper presents an eye opening monitor (EOM) architecture designed for multi-protocol serial link applications, which is operated at the data rate of 1.25-10Gb/s. The proposed two dimensional EOM provides the variable 248 different masks, based on the phase interpolators (PIs) and the digital-to-analog converters (DACs). The horizontal asymmetric masks are also closer to the real eye. The EOM is achieved in 40nm CMOS technology and supplied with 1.1V. The simulated results show that this design can output a frequency corresponding to the bit error rate (BER). The algorithm that is controlled by digital control logic block V_Control and PI_Control can implement traversal of the variable asymmetric sizes of masks. The total power consumption of the EOM is 47 mW at 10Gb/s in this design.

[1]  Fei Yuan,et al.  New 2-D Eye-Opening Monitor for Gb/s Serial Links , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Debesh Bhatta,et al.  A 10Gb/s two dimensional scanning eye opening monitor in 0.18um CMOS process , 2009, 2009 IEEE MTT-S International Microwave Symposium Digest.

[3]  A. Rylyakov,et al.  A 10Gb/s eye-opening monitor in 0.13 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[4]  Lidong Chen,et al.  A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[5]  Chulsoon Hwang,et al.  A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel , 2008, 2008 IEEE International Symposium on Electromagnetic Compatibility.

[6]  Hiroaki Uchida,et al.  A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  John Wu,et al.  A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).