Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures

This paper proposes a reliability evaluation environment for coarse-grained reconfigurable architectures. This environment is designed so that it can be easily extended to different target architectures and applications by automating the generation of the simulation inputs such as HDL codes for fault injection and configuration information. This automation enables us to explore a huge design space in order to efficiently analyze area/reliability trade-offs and find the best solution. This paper also shows demonstrative examples of the design space exploration of coarse-grained reconfigurable architectures using the proposed environment. Through the demonstrations, we discuss relationship between coarse-grained architectures and reliability, which has not yet been addressed in existing literatures and show the feasibility of the proposed environment.

[1]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[2]  Adrian Stoica,et al.  Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[3]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[4]  Bertil Svensson,et al.  Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing , 2009, Microprocess. Microsystems.

[5]  Martin Margala,et al.  Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath , 2009, 2009 22nd International Conference on VLSI Design.

[6]  T. Knight,et al.  Pathfinder : A Negotiation-Based Performance-Driven Router for FPGAs , 2012 .

[7]  Masanori Hashimoto,et al.  Coarse-grained dynamically reconfigurable architecture with flexible reliability , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[8]  I ScottKirkpatrick.  Optimization by Simulated Annealing: Quantitative Studies , 1984 .

[9]  N. Seifert,et al.  Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node , 2009, 2009 IEEE International Reliability Physics Symposium.

[10]  M. Wirthlin,et al.  Improving FPGA Design Robustness with Partial TMR , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[11]  David C. Matthews,et al.  NSEU impact on commercial avionics , 2009, 2009 IEEE International Reliability Physics Symposium.

[12]  Hiroyuki Ochi,et al.  Hot-Swapping architecture extension for mitigation of permanent functional unit faults , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[13]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[14]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[15]  Harry C. Koons,et al.  THE IMPACT OF THE SPACE ENVIRONMENT ON SPACE SYSTEMS , 1999 .