Embedded analog-to-digital converters

Systems-on-Chips (SoCs) have become a reality in the past decade. Several dozens of different functional blocks are being integrated on a single die, reaching transistor counts of up to half a billion. From the Analog portion of an SoC the Data Converters are probably among the most challenging blocks, often limiting system performance and dominating power dissipation. However, requirements regarding yield, die-size, scalability, noise immunity, power and the fact that logic is almost for free, cause distinct differences between embedded Data Converters and their stand-alone, usually general purpose, counterparts. This paper describes these differences and provides an overview of the state-of-the art in Analog-to-Digital Conversion.

[1]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  B. P. Brandt,et al.  A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist , 1999, IEEE J. Solid State Circuits.

[3]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[4]  R.C. Taft,et al.  A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency , 2004, IEEE Journal of Solid-State Circuits.

[5]  B.P. Ginsburg,et al.  Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[6]  P. Hurst,et al.  A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.

[7]  Bang-Sup Song,et al.  A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming , 2000, IEEE Journal of Solid-State Circuits.

[8]  A. Dingwall,et al.  An 8-MHz CMOS subranging 8-bit A/D converter , 1985, IEEE Journal of Solid-State Circuits.

[9]  Sunghyun Park,et al.  A 4-GS/s 4-bit Flash ADC in 0.18- $\mu{\hbox {m}}$ CMOS , 2007, IEEE Journal of Solid-State Circuits.

[10]  P.J. Hurst,et al.  A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[11]  Un-Ku Moon,et al.  "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC , 2006, IEEE Journal of Solid-State Circuits.

[12]  B.P. Ginsburg,et al.  500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC , 2007, IEEE Journal of Solid-State Circuits.

[13]  Michael P. Flynn,et al.  A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS , 2006, IEEE Custom Integrated Circuits Conference 2006.

[14]  Klaas Bult The Effect of Technology Scaling on Power Dissipation in Analog Circuits , 2006 .

[15]  Boris Murmann,et al.  A/D converter trends: Power dissipation, scaling and digitally assisted architectures , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[16]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[17]  Hae-Seung Lee,et al.  A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC , 2007, IEEE Journal of Solid-State Circuits.

[18]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[19]  Yuriy Greshishchev,et al.  A 24GS/s 6b ADC in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[20]  H. Matsui,et al.  A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration , 2006, IEEE Journal of Solid-State Circuits.

[21]  R. J. van de Plassche,et al.  A high-speed 7 bit A/D converter , 1979 .

[22]  K. Bult,et al.  An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2 , 1997, IEEE J. Solid State Circuits.

[23]  Gil-Cho Ahn,et al.  A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR , 2005, VLSIC 2005.

[24]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[25]  Shouli Yan,et al.  A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[26]  Soon-Kyun Shin,et al.  A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[27]  Michiel Steyaert,et al.  Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter , 2003 .

[28]  Robert H. Walden,et al.  Analog-to-digital converter survey and analysis , 1999, IEEE J. Sel. Areas Commun..

[29]  Lei Xie,et al.  A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC , 2006, IEEE Custom Integrated Circuits Conference 2006.

[30]  David A. Johns,et al.  An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage , 2007, ESSCIRC.

[31]  D. Draxelmayr,et al.  A 6b 600MHz 10mW ADC array in digital 90nm CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[32]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[33]  Bram Nauta,et al.  A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[34]  Borivoje Nikolic,et al.  Scaling of analog-to-digital converters into ultra-deep-submicron CMOS , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[35]  I. Opris,et al.  A single-ended 12 b 20 M sample/s self-calibrating pipeline A/D converter , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[36]  Byung-Moo Min,et al.  A 10b 170MS/s CMOS Pipelined ADC Featuring 84dB SFDR without Calibration , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[37]  J. Kornblum,et al.  A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.

[38]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[39]  Byung-Moo Min,et al.  A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC , 2003, IEEE J. Solid State Circuits.

[40]  Pier Andrea Francese,et al.  A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency , 2009, IEEE Journal of Solid-State Circuits.

[41]  Soon-Jyh Chang,et al.  A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[42]  Frank M. L. van der Goes,et al.  A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[43]  Paul Voois,et al.  A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s , 2008, IEEE Journal of Solid-State Circuits.

[44]  I. Galton,et al.  A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.

[45]  R. Brodersen,et al.  Considerations for high-frequency switched-capacitor ladder filters , 1980 .

[46]  P.J. Hurst,et al.  A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration , 2004, IEEE Journal of Solid-State Circuits.

[47]  G. Geelen,et al.  An 8b 600MS/s 200mW CMOS folding A/D converter using an amplifier preset technique , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[48]  D.A. Johns,et al.  A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[49]  Hae-Seung Lee,et al.  Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies , 2006, IEEE Journal of Solid-State Circuits.

[50]  S.H. Lewis,et al.  An 8b 80MSample/s pipelined ADC with background calibration , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[51]  A. Montijo,et al.  A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[52]  K. Bult Broadband communication circuits in pure digital deep sub-micron CMOS , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[53]  Hae-Seung Lee,et al.  Comparator-based switched-capacitor circuits for scaled CMOS technologies , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[54]  I. Ahmed,et al.  A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold , 2008, IEEE Journal of Solid-State Circuits.

[55]  Stephen H. Lewis,et al.  A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers , 1997, IEEE J. Solid State Circuits.

[56]  R. C. Taft,et al.  A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V , 2001 .

[57]  Ivan Prudyus,et al.  IEEE International Solid-State Circuits Conference , 2008 .

[58]  Lei Xie,et al.  A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications , 2008, IEEE Journal of Solid-State Circuits.

[59]  K. Bult,et al.  Analog design in deep sub-micron CMOS , 2000, Proceedings of the 26th European Solid-State Circuits Conference.