Power-Gating Models for Rapid Design Exploration

Power gating (PG) is an effective method to reduce leakage currents in an SoC design during run-time. It dynamically shuts down components using a network of sleep transistors but requires a detailed analysis to scale this network appropriately with respect to area wake-up time in-rush currents voltage drops and transition energies. In this paper we present a method to efficiently determine these key parameters for any SoC design and sleep transistor network at gate-level to enable the rapid exploration of power design alternatives while providing sufficient accuracy for high-level design exploration. Compared to SPICE our approach achieves a speed-up of up to 11457x for two ISCAS circuits a 32-bit multiplier and a RISC-V core each build for a 90nm PDK. The average error compared to SPICE is 2.6% for peak current and 10% for wake-up energy and delay.

[1]  Shih-Chieh Chang,et al.  An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Lei He,et al.  Distributed sleep transistor network for power reduction , 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Olivier Sentieys,et al.  Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters , 2011, 2011 24th Internatioal Conference on VLSI Design.

[4]  David Howard,et al.  Challenges in sleep transistor design and implementation in low-power designs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[5]  Vineet Sahula,et al.  Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits , 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

[6]  Fei Li,et al.  Estimation of maximum power-up current , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[7]  Ranga Vemuri,et al.  Dynamic virtual ground voltage estimation for power gating , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[8]  Ranga Vemuri,et al.  Dynamic Characteristics of Power Gating During Mode Transition , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Taewhan Kim,et al.  Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Olivier Sentieys,et al.  A semiempirical model for wakeup time estimation in power-gated logic clusters , 2012, DAC Design Automation Conference 2012.

[11]  Chien-Nan Jimmy Liu,et al.  Peak wake-up current estimation at gate-level with standard library information , 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

[12]  Vazgen Melikyan,et al.  Synopsys' open educational design kit: Capabilities, deployment and future , 2009, 2009 IEEE International Conference on Microelectronic Systems Education.

[13]  Fei Li,et al.  High-level area and power-up current estimation considering rich cell library , 2004 .