This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated- circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented. I. INTRODUCTION UBSTRATE coupling has received attention recently from mixed analog-digital designers and radio-frequency de- signers attempting to integrate sensitive low-noise circuits on the same substrate as noise-generating or switching circuits. Single-chip or highly integrated implementations of complex systems provide several advantages, such as reduced package count and reduced power dissipation due to a reduction in package pin and bond-wire capacitance. Further, routing high- frequency signals off-chip often requires a 50 ohm impedance- match, which can result in a higher power dissipation com- pared to a highly integrated solution. Other advantages include a reduction in cost and improved high-frequency performance due to reduced package interconnect parasitics. A major disadvantage of higher levels of integration is the increased interaction between circuits. This interaction can appear in two major ways. it can occur due to the significant mutual inductance and capacitance which exist between any two bond-wires and pins in a package. The second cause of interaction is the nonideal isolation provided by the common substrate shared by devices in an integrated circuit. Currents can flow through the substrate due to the nonzero dielectric constant and conductivity of the substrate material and couple circuits located in different parts of the substrate. The latter problem, referred to as substrate coupling, is discussed in this paper.
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