Fault studies of MMC-HVDC links using FPGA and CPU on a real-time simulator with iteration capability

The detailed real-time simulation of MMC-based HVDC links is one of the most challenging tasks in power system validation today, requiring the combined use of CPU and FPGA technologies. The inclusion of surge arresters in the real-time fault tests further increases the difficulties because of the highly non-linear characteristics of such protective devices. In this paper, the OPAL-RT digital real-time simulator (DRTS) with the iteration capable State-Space-Nodal (SSN) solver is demonstrated to be accurate in such fault testing conditions. Two test cases are used for this purpose: an MMC-HVDC link based on the 401-level France-Spain link and a 271-level MMC system working in STATCOM mode.

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