Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning

Interlayer liquid cooling network has been considered as one of the effective cooling mechanisms for heat dissipation in three dimensional integrated circuits (3D ICs). In this paper, an optimization approach is proposed for 3D IC interlayer cooling network design with consideration of cooling energy minimization and thermal constraints. First, a channel patterning technique is proposed which adopts straight-channel patterns and corner-barrier patterns to efficiently reduce the temperature of hotspots in the chip. Second, an iterative channel pruning process is proposed for cooling network optimization that reduces the temperature gradient and cooling energy. Furthermore, algebraic multigrid-preconditioned generalized conjugate residual solver is applied for thermal simulation in this optimization process to achieve better computational efficiency. Experimental results have shown that the proposed optimization approach can produce optimal interlayer cooling networks with 11.3%–61.3% cooling energy savings and 49.3%–59.4% pumping pressure savings in comparison with the first place winner of 2015 computer-aided design contest at International Conference on Computer-Aided Design.

[1]  Ankur Srivastava,et al.  Non-uniform micro-channel design for stacked 3D-ICs , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[2]  James Demmel,et al.  A Supernodal Approach to Sparse Partial Pivoting , 1999, SIAM J. Matrix Anal. Appl..

[3]  Y. Notay.  An aggregation-based algebraic multigrid method , 2010 .

[4]  J. Meindl,et al.  A 3D-IC Technology with Integrated Microchannel Cooling , 2008, 2008 International Interconnect Technology Conference.

[5]  Gabriela Nicolescu,et al.  Explicit transient thermal simulation of liquid-cooled 3D ICs , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[6]  Gokhan Memik,et al.  TESLA: Using microfluidics to thermally stabilize 3D stacked STT-RAM caches , 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

[7]  Ankur Srivastava,et al.  TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs , 2012, ISPD '12.

[8]  Ankur Srivastava,et al.  Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling , 2016, FPGA.

[9]  M. Bakir,et al.  3D stacked microfluidic cooling for high-performance 3D ICs , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[10]  David Atienza,et al.  GreenCool: An Energy-Efficient Liquid Cooling Design Technique for 3-D MPSoCs Via Channel Width Modulation , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Martin Burtscher,et al.  Bridging the processor-memory performance gap with 3D IC technology , 2005, IEEE Design & Test of Computers.

[12]  Timothy A. Davis,et al.  Algorithm 907 , 2010 .

[13]  S. Kandlikar.  Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits , 2014 .

[14]  John L. Bresina,et al.  Heuristic-Biased Stochastic Sampling , 1996, AAAI/IAAI, Vol. 1.

[15]  David Atienza,et al.  3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[16]  Chip-Hong Chang,et al.  An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits , 2013, Integr..

[17]  Artem Napov,et al.  An Algebraic Multigrid Method with Guaranteed Convergence Rate , 2012, SIAM J. Sci. Comput..

[18]  Yvan Notay,et al.  Aggregation-Based Algebraic Multigrid for Convection-Diffusion Equations , 2012, SIAM J. Sci. Comput..

[19]  Yusuf Leblebici,et al.  Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks , 2009, 2009 IEEE International Conference on 3D System Integration.