A charge recycling differential noise immune perceptron

Abs.

[1]  Samuel D. Naffziger,et al.  The implementation of the Itanium 2 microprocessor , 2002, IEEE J. Solid State Circuits.

[2]  S. Bobba,et al.  Current-mode threshold logic gates , 2000, Proceedings 2000 International Conference on Computer Design.

[3]  Wulfram Gerstner,et al.  Reduction of the Hodgkin-Huxley Equations to a Single-Variable Threshold Model , 1997, Neural Computation.

[4]  V. Beiu,et al.  Ultra-fast noise immune CMOS threshold logic gates , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[5]  Stamatis Vassiliadis,et al.  A new latch-based threshold logic family , 2001, 2001 International Semiconductor Conference. CAS 2001 Proceedings (Cat. No.01TH8547).

[6]  Mohamed I. Elmasry,et al.  SC2L: a low-power high-performance dynamic differential logic family , 1999, ISLPED '99.

[7]  K. Goser,et al.  A low-power and high-performance CMOS fingerprint sensing and encoding architecture , 1998, Proceedings of the 24th European Solid-State Circuits Conference.

[8]  Valeriu Beiu,et al.  Differential implementations of threshold logic gates , 2003, Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on.

[9]  Wonchan Kim,et al.  Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic , 2001 .

[10]  Kwyro Lee,et al.  Charge recycling differential logic for low-power application , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[11]  M. G. Johnson A symmetric CMOS NOR gate for high-speed applications , 1988 .

[12]  C. Pacha,et al.  Aspects of systems and circuits for nanoelectronics , 1997, Proc. IEEE.

[13]  Said F. Al-Sarawi,et al.  Low power, high speed, charge recycling CMOS threshold logic gate , 2001 .

[14]  A. Afzali-Kusha,et al.  No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[15]  Akira Matsuzawa,et al.  A low power signal-swing suppressing strategy using time-multiplexed differential data-transfer (TMD) scheme , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[16]  Young-Hyun Jun,et al.  CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI , 2003 .

[17]  Werner Weber,et al.  A low-power and high-performance CMOS fingerprint sensing and encoding architecture , 1999 .

[18]  Wonchan Kim,et al.  Current sensing differential logic: a CMOS logic for high reliability and flexibility , 1999 .

[19]  Sung-Mo Kang,et al.  CMOS Pass-gate No-race Charge-recycling Logic (CPNCL) , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[20]  A. Gago,et al.  New types of digital comparators , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[21]  J. C. Tejero,et al.  A threshold logic gate based on clocked coupled inverters , 1998 .

[22]  A. Matsuzawa,et al.  A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme , 1996 .

[23]  W S McCulloch,et al.  A logical calculus of the ideas immanent in nervous activity , 1990, The Philosophy of Artificial Intelligence.

[24]  Yusuf Leblebici,et al.  A capacitive threshold-logic gate , 1996, IEEE J. Solid State Circuits.

[25]  Young-Hyun Jun,et al.  A true single-phase clocking scheme for low-power and high-speed VLSI , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[26]  Stamatis Vassiliadis,et al.  Capacitive threshold logic: a designer perspective , 1999, CAS '99 Proceedings. 1999 International Semiconductor Conference (Cat. No.99TH8389).

[27]  Roland Strandberg,et al.  Single input current-sensing differential logic (SCSDL) , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[28]  G. R. Hellestrand,et al.  Dynamic half rail differential logic for low power , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[29]  Derek Abbott,et al.  Compact parallel (m,n) counters based on self-timed threshold logic , 2002 .

[30]  A. Afzali-Kusha,et al.  Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications , 2003, Southwest Symposium on Mixed-Signal Design, 2003..

[31]  José Fernández-Ramos,et al.  A Balanced Capacitive Threshold-Logic Gate , 2004 .

[32]  Kaushik Roy,et al.  Differential Current Switch Logic: A Low Power DCVS Logic Family , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[33]  Bai-Sun Kong,et al.  Asynchronous sense differential logic , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[34]  Kiyoung Choi,et al.  Modified half rail differential logic for reduced internal logic swing , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[35]  Valeriu Beiu A survey of perceptron circuit complexity results , 2003, Proceedings of the International Joint Conference on Neural Networks, 2003..

[36]  Kwyro Lee,et al.  Charge recycling differential logic (CRDL) for low power application , 1996 .

[37]  Hiroki Morimura,et al.  A 1-V 1-Mb SRAM for portable equipment , 1996, ISLPED.

[38]  Werner Weber,et al.  On the application of the Neuron MOS transistor principle for modern VLSI design , 1996 .

[39]  K.Y. Cheung CRRDL: a novel charge recovery-recycling differential logic , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[40]  Dimitris Anastassiou,et al.  Switched-capacitor neural networks , 1987 .

[41]  Tadahiro Ohmi,et al.  An intelligent MOS transistor featuring gate-level weighted sum and threshold operations , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[42]  A. Inoue,et al.  A low power SOI adder using reduced-swing charge recycling circuits , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[43]  Hongchin Lin,et al.  A low-power 3-phase half rail pass-gate differential logic , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[44]  Sung-Mo Kang,et al.  Modular charge recycling pass transistor logic (MCRPL) , 2000 .

[45]  Maria J. Avedillo,et al.  Low-power CMOS threshold-logic gate , 1995 .

[46]  Valeriu Beiu,et al.  VLSI implementations of threshold logic-a comprehensive survey , 2003, IEEE Trans. Neural Networks.

[47]  Tadashi Shibata,et al.  Clock-controlled neuron-MOS logic gates , 1998 .

[48]  Valeriu Beiu,et al.  On higher order noise immune perceptrons , 2001, IJCNN'01. International Joint Conference on Neural Networks. Proceedings (Cat. No.01CH37222).

[49]  P. Celinski,et al.  Delay analysis of neuron-MOS and capacitive threshold-logic , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).