Recent Advances on Linear Low-Dropout Regulators
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[1] Edgar Sanchez-Sinencio,et al. Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison , 2014, IEEE Circuits and Systems Magazine.
[2] Ke-Horng Chen,et al. High-PSR-bandwidth capacitor-free LDO regulator with 50µA minimized load current requirement for achieving high efficiency at light loads , 2008 .
[3] Arijit Raychowdhury,et al. Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits , 2018, IEEE Journal of Solid-State Circuits.
[4] Jiann-Jong Chen,et al. A capacitor-free fast-transient-response LDO with dual-loop controlled paths , 2007, 2007 IEEE Asian Solid-State Circuits Conference.
[5] Zeynep Toprak-Deniz,et al. Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS , 2020, IEEE Journal of Solid-State Circuits.
[6] K. Entesari,et al. High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique , 2010, IEEE Journal of Solid-State Circuits.
[7] Gyu-Hyeong Cho,et al. A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor , 2017, IEEE Journal of Solid-State Circuits.
[8] Mohammad A. Al-Shyoukh,et al. A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation , 2007, IEEE Journal of Solid-State Circuits.
[9] Edgar Sánchez-Sinencio,et al. Full On-Chip CMOS Low-Dropout Voltage Regulator , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[10] Rui P. Martins,et al. An Analog-Proportional Digital-Integral Multiloop Digital LDO With PSR Improvement and LCO Reduction , 2020, IEEE Journal of Solid-State Circuits.
[11] Patrick P. Mercier,et al. A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM , 2020, IEEE Journal of Solid-State Circuits.
[12] Bertan Bakkaloglu,et al. A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] Seng-Pan U,et al. An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator , 2018, IEEE Journal of Solid-State Circuits.
[14] Mingoo Seok,et al. A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture , 2017, IEEE Journal of Solid-State Circuits.
[15] Wei Shu,et al. A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range , 2018, IEEE Journal of Solid-State Circuits.
[16] Philip K. T. Mok,et al. A Capacitor-Less CMOS Active Feedback Low-Dropout Regulator With Slew-Rate Enhancement for Portable On-Chip Application , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.
[17] In-Chul Hwang,et al. Fast Transient Fully Standard-Cell-Based All Digital Low-Dropout Regulator With 99.97% Current Efficiency , 2018, IEEE Transactions on Power Electronics.
[18] Yuanjin Zheng,et al. A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications , 2020, IEEE Journal of Solid-State Circuits.
[19] Bertan Bakkaloglu,et al. A 1.24 $\mu$ A Quiescent Current NMOS Low Dropout Regulator With Integrated Low-Power Oscillator-Driven Charge-Pump and Switched-Capacitor Pole Tracking Compensation , 2018, IEEE Journal of Solid-State Circuits.
[20] James Tschanz,et al. 14.7 A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).
[21] Vadim V. Ivanov. Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise , 2009 .
[22] Vivek De,et al. A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response , 2020, IEEE Journal of Solid-State Circuits.
[23] K. Leung,et al. A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation , 2003, IEEE J. Solid State Circuits.
[24] Gabriel A. Rincon-Mora,et al. A low-voltage, low quiescent current, low drop-out regulator , 1998, IEEE J. Solid State Circuits.
[25] Philip K. T. Mok,et al. Wide-Loading-Range Fully Integrated LDR With a Power-Supply Ripple Injection Filter , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.
[26] Kazunori Watanabe,et al. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS , 2010, IEEE Custom Integrated Circuits Conference 2010.
[27] Gabriel A. Rincón-Mora,et al. A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[28] Patrick P. Mercier,et al. A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control , 2018, IEEE Journal of Solid-State Circuits.
[29] T. Karnik,et al. Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.
[30] Jaehyouk Choi,et al. An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique , 2018, IEEE Journal of Solid-State Circuits.
[31] Pui Ying Or,et al. An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection , 2010, IEEE Journal of Solid-State Circuits.
[32] Arijit Raychowdhury,et al. All-Digital Low-Dropout Regulator With Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits , 2016, IEEE Transactions on Power Electronics.
[33] Gabriel A. Rincón-Mora,et al. Analysis and design of monolithic, high PSR, linear regulators for SoC applications , 2004, IEEE International SOC Conference, 2004. Proceedings..
[34] In-Chul Hwang,et al. Capacitorless Self-Clocked All-Digital Low-Dropout Regulator , 2019, IEEE Journal of Solid-State Circuits.
[35] Siew Kuok Hoon,et al. A CMOS Low Noise, Chopper Stabilized Low-Dropout Regulator With Current-Mode Feedback Error Amplifier , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[36] José Silva-Martínez,et al. A frequency compensation scheme for LDO voltage regulators , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[37] Chenchang Zhan,et al. An output-capacitor-free cascode low-dropout regulator with low quiescent current and high power supply rejection , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.
[38] José Silva-Martínez,et al. External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range , 2014, IEEE Journal of Solid-State Circuits.
[39] Shi-Jie Wen,et al. A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer , 2019, IEEE Journal of Solid-State Circuits.
[40] Wing-Hung Ki,et al. 17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[41] Chulwoo Kim,et al. A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance , 2020, IEEE Journal of Solid-State Circuits.
[42] Quan Pan,et al. A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.
[43] Xiaosen Liu,et al. A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency , 2020, 2020 IEEE Symposium on VLSI Circuits.
[44] Ka Nang Leung,et al. A Low-Dropout Regulator for SoC With $Q$-Reduction , 2007, IEEE Journal of Solid-State Circuits.
[45] KiWing-Hung,et al. Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips , 2010 .